(1). Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a programmable read only memory device used in an electronic device, such as an electronic computer.
(2). Prior Art
In general, a programmable read only memory (P-ROM) device which is one of the semiconductor memory devices, consists of a matrix, which is formed by a cross structure of a plurality of bit lines and a plurality of word lines, and a memory cell at each cross position of the matrix. The memory cell consists of either a series circuit of two diodes of opposite polarity or a series circuit of a fuse and a diode connected between the bit line and the word line. The writing-in of information to this memory device is effected by either bringing one of the two diodes to a short-circuit status or by fusing the fuse, due to the supply of a writing-in current, to the selected bit and word lines connecting circuit. The value of this writing-in current is, for example, about 100 mA to 200 mA, which is more than a hundred times greater than the reading-out current, the value of which is about 0.5 mA.
In the prior art, a decorder driver circuit is connected at the end of the above mentioned word line to which the memory cells are connected. The writing-in current flows into this decoder driver circuit. In this prior art circuit structure, a current sink capacity, which enables the absorption of a large writing-in current, is required for this decoder driver circuit. To meet this requirement, this decoder driver circuit comprises a great number of large transistors and like elements and includes a great number of related connecting conductors so that the decoder driver circuit is big in size and complicated in structure. If such a big and complicated decoder driver circuit is used, the occupying area of the circuit pattern in the semiconductor device which forms the memory device is increased, the parasitic capacitance in the memory is increased and thus the operation time is lengthened. Accordingly a problem in the prior art memory device is that, it is difficult to increase the reading-out speed of the memory. Another problem in the prior art memory is that it is difficult to increase the degree of integration (information storing capacity) of memory cells in a semiconductor device having a predetermined reading-out speed, because the decoder driver circuit occupies its own space.
With regard to the above described prior art memory, an example of the read only memory devices of the combined diode type is disclosed in U.S. Pat. No. 3,742,592, an example of the read only memory devices of the fuse type is disclosed in U.S. Pat. No. 3,147,461 and an introductory explanation regarding bipolar RAM and ROM is found in the Proceedings of the Institute of Electronics and Communication Engineers of Japan Vol. 60, No. 11, Nov. 1957, pages 1252 through 1257.
Another prior art P-ROM type semiconductor memory device is disclosed in Laid-open Japanese Patent Application No. 52-71183 (priority date: Dec. 5, 1975, France, No. 7537358) in which the memory cell consists of a lateral PNP type transistor and a PN junction diode or a fuse. This lateral PNP type transistor consists of an N type epitaxial layer, which forms a word line, formed on a P type semiconductor substrate and with P type regions formed separately in the N type epitaxial regions. In this memory device, the writing-in of the information is effected by passing a writing-in current from a selected bit line through the PN junction diode or fuse connected to the bit line, the lateral PNP type transistor and a shunt which is parallel with the bit line. Accordingly, the writing-in current to a memory cell located remote from the shunt passes through a lateral PNP type transistor which is loated between the memory cell and the shunt and is formed by a P type region forming other memory cells, in case where the writing-in current passes between a bit line connected to the memory cell and the shunt.
Accordingly, in this prior art memory device, the energy for writing-in the information into the selected memory cell connected to a bit line varies in accordance with the position of the selected bit line during writing-in of the information. Therefore, it is necessary to determine the ability of the writing-in circuit so that the writing-in into the memory cell connected to the bit line located at the remotest position is possible. However, this causes a reduction in the degree of integration for a semiconductor memory device of greater capacity. In addition, the shunt reduces the degree of integration for a semiconductor memory device.